IS42S32400B |
RFQ for IS42S32400B Required Field |
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| Technical/Catalog Information | IS42S32400B-6B |
| Vendor | ISSI, Integrated Silicon Solution Inc |
| Category | Integrated Circuits (ICs) |
| Memory Type | SDRAM |
| Memory Size | 128M (4Mx32) |
| Speed | 166MHz |
| Interface | Parallel |
| Package / Case | 90-FBGA |
| Packaging | Tray |
| Voltage - Supply | 3 V ~ 3.6 V |
| Operating Temperature | 0°C ~ 70°C |
| Format - Memory | RAM |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | IS42S32400B 6B IS42S32400B6B |
| Product | Manufacturers | Pack | D/C |
| IS42S32400B | - | - | - |
The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row.Inputs A0-A7 provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. The row will remain open for subsequent accesses when AUTO PRECHARGE is not selected. DQ's read data is subject to the logic level on the DQM inputs two clocks earlier. When a given DQM signal was registered HIGH, the corresponding DQ's will be High-Z two clocks later. DQ's will provide valid data when the DQM signal was registered LOW.
A burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank, and the starting column location is provided by inputs A0-A7.Whether or not AUTO-PRECHARGE is used is determined by A10.
The row being accessed will be precharged at the end of the WRITE burst, if AUTO PRECHARGE is selected. If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses.
A memory array is written with corresponding input data on DQ's and DQM input logic level appearing at the same time.Data will be written to memory when DQM signal is LOW. When DQM is HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.
Features |
| • Clock frequency: 166, 143, 125, 100 MHz• Fully synchronous; all signals referenced to a positive clock edge• Internal bank for hiding row access/precharge• Power supply VDD VDDQIS42S32400B 3.3V 3.3V• LVTTL interface• Programmable burst length (1, 2, 4, 8, full page)• Programmable burst sequence:Sequential/Interleave• Auto Refresh (CBR)• Self Refresh with programmable refresh periods• 4096 refresh cycles every 64 ms• Random column address every clock cycle• Programmable CAS latency (2, 3 clocks)• Burst read/write and burst read/single write operations capability• Burst termination by burst stop and precharge command• Available in Industrial Temperature• Available in 86-pin TSOP-II and 90-ball FBGA• Available in Lead-free |
| Symbol | Parameters | Rating | Unit |
| VDD MAX | Maximum Supply Voltage | 0.5 to +4.6 | V |
| VDDQ MAX | Maximum Supply Voltage for Output Buffer | 0.5 to +4.6 | V |
| VIN | Input Voltage | 0.5 to VDD + 0.5 | V |
| VOUT | Output Voltage | 1.0 to VDDQ + 0.5 | V |
| PD MAX | Allowable Power Dissipation | 1 | W |
| ICS | Output Shorted Current | 50 | mA |
| TOPR | Operating Temperature Com. Ind. |
0 to +70 40 to +85 |
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| TSTG | Storage Temperature | 65 to +150 |
